Experience
- Postdoctoral Researcher, Indian Institute of Technology (Indian School of Mines), Dhanbad, Jharkhand, India, from August, 2024 – July 2025
- Research Associate, Indian Institute of Science (IISc) Bangalore, Karnataka, India, from Feb, 2024 - March, 2024.
- Project Associate, Indian Institute of Science (IISc) Bangalore, Karnataka, India, from August, 2022 - Jan, 2024.
- Associate Engineer (IP Design, FPGA Team) Collins Aerospace (Raytheon Technologies) Bangalore, Karnataka, India, from Nov, 2021 - Jul 2022.
- Teaching Assistant FPGA based system design, System on Chip design, and ASIC and CAD Laboratory, National Institute of Technology (NIT) Nagaland, India from Jan 2018 – Oct 2021
- Lecturer Triumphant Institute of Management Education Pvt. Ltd, Guwahati, Assam, India, from Jul 2016–Jan 2018.
Teachings
- CS13113: Digital Logic Design
- CS13213: Digital Logic Design Laboratory
- AI13103: Digital Logic Design
- AI13203: Digital Logic Design Laboratory
- EC17116: Elective I: VLSI Design
- EC17216: Modeling and Testing of Digital Systems Laboratory
- ZZ13201: Professional Practice I
Education
- PhD (Electronics and Communication Engineering, National Institute of Technology, Nagaland, India)
- M.Tech. (Electronics Engineering, Banasthali University, Rajasthan, India)
- B.Tech (Electronics and Communication Engineering, Vinoba Bhave University, Hazaribagh, Jharkhand)
Contact Address :
Department of Electronics and Communication Engineering,
NIT Sikkim,
Ravangla Campus, South Sikkim,Pin-737139
India.
Journals/Book Chapters
- Jayshree, G. Seetharaman and D. Pati, ‘Energy consumption and Performance Comparison of DE Optimization and PSO-based IP-core Mapping Technique for 2-D and 3-D Network-on-Chip,’ Semiconductor Science and Technology, vol. 36, no. 8, p. 085 015, 2021. DOI: 10.1088/1361-6641/ac038c.
- Jayshree, G. Seetharaman and D. Pati, ‘Enhanced TACIT Encryption and Decryption Algorithm for Secured Data Routing in 3D Network-on-Chip based Interconnection of SoC for IoT Application,’ Journal of Scientific and Industrial Research (JSIR), CSIR-NISCAIR, vol. 80, pp. 520–527, 2021. DOI: 10.56042/jsir.v80i6.38356
- Jayshree, G. Seetharaman and D. Pati, ‘Design and Analysis of Area Performance and Energy Consumption of Network-on-Chip Point-to-Point and Bus Interconnect for SoC,’ Journal of IEI; Springer. DOI: 10.1007/s40031-022-00735-5
- Jayshree, G. Seetharaman and D. Pati, ‘Comparative Study of Hybrid Optimizations Technique for On-chip Interconnect in Multimedia SoCs,’ Smart Intelligent Computing and Communication Technology in IOS Press, 2021. DOI: 10.3233/APC210069
- Jayshree, G. Seetharaman and D. Pati, ‘Reliable Fault-tolerance Routing Technique for Network on chip Interconnect,’ Lecture Notes in Networks and Systems, Springer, 2021. DOI: 10.1007/978-981-16-2422-3_60.
- Jayshree, G. Seetharaman and J. Kumar, ‘Adaptive congestion-aware high performance scalable 2-d and 3-d topologies for network-on-chip based interconnect for quantum computing,’ Microprocessors and Microsystems 2025. (Under review)
- Jayshree and J. Kumar, ‘Unveiling role of wetting layer on the optimum transition energy of InAs/GaAs quantum dots,’ Semiconductor Science and Technology 2025. (Under review)
Conference
- J. Jayshree and J. Kumar, "Unveiling Role of Size, Wet Layer Thickness, and Interface Potential Barrier on the Confinement Effect of the Conical, Cylindrical and Spherical Quantum Dots," 2025 IEEE 1st International Conference on Smart and Sustainable Developments in Electrical Engineering (SSDEE), Dhanbad, India, 2025, pp. 1-7, doi: 10.1109/SSDEE64538.2025.10968957
- R. R. Malik, A. N. Shaji, Jayshree et al., ‘Interplay of Surface Passivation and Electric Field in Determining ESD Behaviour of p-GaN gated AlGaN/GaN HEMTs,’ in 2023 45th Annual EOS/ESD Symposium (EOS/ESD), vol. EOS-45, 2023, pp. 1–7. DOI: 10.23919/EOS/ESD58195.2023.10287740
- Jayshree, G. Seetharaman and D. Pati, ‘Design of High Performance HMRPD Network on Chip Interconnect for Neuromorphic Architectures,’ NIT Meghalaya, India, ICEPE, 2021, 1–4. DOI: 10.1109/ICEPE50861.2021.9404379.
- Jayshree and G. Seetharaman, ‘Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay,’ The University of Edinburgh, United Kingdom., NASA/ESA Conference on AHS, 2018, 204–209. DOI: 10.1109/AHS.2018.8541441.
- Jayshree, et.al ‘Modeling and Simulation of AlGaN/GaN Heterojunction-FET using Silvaco TCAD Tools,’ MRSI Symposium, CSIR-North East Institute of Science Technology, Jorhat, Assam, INDIA, 2016.
- Jayshree, ‘Advanced Approach for optimizing ESD Protection Device using Layout Parameter Variation Technique,’ Indian Institute of Technology (IIT) Guwahati, India., Annual Chemical Engineering Symposium (Reflux), 2016.
- Jayshree, ‘Design and Simulation of ggNMOS Protected Circuit for LVDS Transmitter using 180 nm Technology,’ Indian Institute of Technology (IIT) Jodhpur & Defence Laboratory Jodhpur, India., National Conference on Semiconductor Materials and Devices, 2016.
- Jayshree, S. Verma and A. Chatterjee, ‘Design of LVDS Receiver at 2 gbps using 0.18 μm CMOS Technology with ESD Protection Device,’ National Institute of Technology Patna, India, International Conference on Multifunctional Materials for Device Application (ICMDA), 2016.
- Jayshree, S. Verma and A. Chatterjee, ‘A Methodology for Designing LVDS Interface System,’ IIT Patna, India., International Symposium on Embedded Computing and System Design (ISED), 2016, 284–288.
- Jayshree, et.al ‘Real-Time Hand Gesture Recognition Technology with Hand Data Glove Through HCI,’ Indian Institute of Technology (IIT) Guwahati, India, Reflux, 2017.
- Jayshree, et.al ‘Devices and Display Energy Saving Technologies: Organic Light Emitting Diode OLED,’ Indian Institute of Technology (IIT) Jodhpur & Defence Laboratory Jodhpur, India., National Conference on Semiconductor Materials and Devices, 2016.
jayshree@nitsikkim.ac.in 
7903493911 